1. Field of the Invention
This invention relates generally to a class of non-volatile memory devices referred to as flash electrically erasable programmable read-only memory (flash EEPROM). More particularly, this invention relates to methods and means to erase digital data from a flash EEPROM cell and for eliminating trapped charges from the flash EEPROM cell.
2. Description of Related Art
The structure and application of the flash EEPROM is well known in the art. The Flash EEPROM provides the density advantages of an erasable programmable read-only memory (EPROM) that employs ultraviolet light to eliminate the programming with the speed of a standard EEPROM. FIG. 1a illustrates a cross-sectional view of a flash EEPROM cell of the prior art. The flash EEPROM cell 10 is formed within a p-type substrate 12. An n.sup.+ drain region 14 and an n.sup.+ source region 16 is formed within the p-type substrate 12.
A relatively thin gate dielectric 36 is deposited on the surface of the p-type substrate 12. The thin gate dielectric 36 is also referred to as a tunneling oxide, hereinafter. A poly-crystalline silicon floating gate 32 is formed on the surface of the gate dielectric 36 above the channel region 34 between the drain region 14 and source region 16. An interpoly dielectric layer 30 is placed on the floating gate 32 to separate the floating gate 32 from a second layer of poly-crystalline silicon that forms a control gate 28.
A p.sup.+ diffusion 18 is placed in the p-type substrate 12 to provide a low resistance path from a terminal 20 to the p-type substrate. The terminal 20 is attached to a substrate voltage generator Vsub. In most applications of an EEPROM, the substrate voltage generator Vsub is set to the ground reference potential (0V).
The source region 16 is connected to a source voltage generator VS through the terminal 22. The control gate 28 is connected through the terminal 26 to the control gate voltage generator VG. And the drain region 14 is connected through the terminal 24 to the drain voltage generator VD.
According to conventional operation, the flash EEPROM cell 10 is programmed by setting the gate control voltage generator VG to a relatively high voltage (on the order of 10V). The drain voltage generator VD is set to a moderately high voltage (on the order of 5V), while the source voltage generator VS is set to the ground reference potential (0V).
With the voltages as described above, hot electrons are produced in the channel 34 near the drain region 14. These hot electrons have sufficient energy to be accelerated across the gate dielectric 36 and trapped on the floating gate 32. The trapped hot electrons cause the threshold voltage of the field effect transistor (FET) that is formed by the flash EEPROM cell 10 to be increased by three to five volts. This change in threshold voltage by the trapped hot electrons causes the cell to be programmed.
During the programming process, some of the hot electrons are trapped 42 in the tunneling oxide 36 or in surface states 40 at the surface of the p-type substrate 12. These trapped electrons cause the threshold voltage of the erased flash EEPROM cell 10 to increase.
To perform a channel erase of the flash EEPROM cell 10 of the prior art, as shown in FIG. 2a, a moderately high positive voltage (on the order of 5V) is generated by the substrate voltage generator Vsub 20. Concurrently, the gate control voltage generator VG is set to a relatively large negative voltage (on the order of -10V). The drain voltage generator VD is usually disconnected from the terminal 24 to allow the drain region 14 to float. The source voltage generator VS is usually disconnected from the source region 16 to allow the source region 16 to float. Under these conditions there is a large electric field developed across the tunneling oxide 36 in the source region 16. This field causes the electrons trapped in the floating gate 32 to be extracted to the channel region 34 by the Fowler-Nordheim tunneling.
FIG. 1b describes an alternate structure of a non-volatile semiconductor memory device of the prior art having a floating gate 32. The memory device is constructed with a n-well 47 diffused into the semiconductor substrate 12 and a p-well 45 diffused into the n-well 47. The source region 16 and drain 14 are then diffused into the p-well 45 with a floating gate 32 and control gate 28 disposed on the surface of the semiconductor substrate much as described in FIG. 1a. The erasure process, as shown in FIG. 2a, involves applying a positive voltage (approximately +5.0V) to the p-well 45 forcing the control gate to a relatively large negative voltage (approximately -10V), and floating the drain 14 and source 16. Generally, the substrate is set to the ground reference potential while the n-well 47 is allowed to float.
U.S. Pat. No. 5,726,933 (Lee et al. 933) describes a method for erasing a flash EEPROM cell 10 as shown in FIG. 1b. The method for erasing of Lee et al. 933 is for eliminating cycling-induced electron trapping in the tunneling oxide 36 of the flash EEPROM cell. The method of Lee et al. 933, as shown in FIG. 2b, begins by setting the control gate voltage generator VG to apply a relatively large clipped sinusoidal negative pulse (approximately -10V) to the control gate 28. The source voltage generator VS is set to a apply a low positive voltage level (approximately 4.3V) to the source region 16. The drain region 14 is allowed to float and the p-well voltage generator Vpw is set to apply a ground reference potential to the p-well 45.
The relatively large clipped sinusoidal negative voltage has three phases. The first phase is an initial decreasing sinusoid that starts at the initial reference voltage (0V) and decreases according to a sine function to the maximum negative voltage (approximately -10V). The second phase is the clipped peak phase where the voltage remains at the maximum negative voltage (approximately -10V). The third phase is a final increasing sinusoid that starts at the maximum negative voltage and increases to the initial reference voltage. The first phase has a duration of from approximately 20 milliseconds to approximately 100 milliseconds. The second phase has a duration of from approximately 100 milliseconds to approximately 500 milliseconds. The third phase has a duration of from 20 milliseconds to approximately 100 milliseconds.
Referring back to FIG. 1b, during the erasure process, not all the hot electrons 42 trapped in the tunneling oxide 36 nor all the surface states 40 are removed. As can be seen in FIG. 3, after performing program/erase cycling, the programming threshold voltage 50 decreases 52 over time. The erase threshold voltage 55 remains relatively constant over the program/erase cycling.